The invention relates to a circuit and an associated method for the erasure or programming of a memory cell. The invention is especially useful for electrically programmable and erasable, non-volatile type memories, such as EEPROMS, flash EPROMS and other similar memories.
A main component of a memory cell of these memories is a floating-gate storage transistor comprising a drain, a source, a control gate and a floating gate that stores information. The programming of a memory cell is usually carried out in two steps: an erasing step followed by a writing step.
To carry out a memory cell erasure step, a high voltage is applied to the control gate of the storage transistor and zero voltage is applied to the drain and source. Thus, the potential difference between the control gate and the drain of the storage transistor sets up an electrical field across the control gate and the drain. This causes electrons to migrate from the source and the drain to the floating gate, and therefore, results in the discharging of the floating gate.
Conversely, to carry out a memory cell write step, zero voltage is applied to the control gate of the storage transistor and a high voltage is applied the drain. The source is taken to a floating potential. The potential difference across the control gate and the drain of the storage transistor creates an electrical field with opposite polarity. This causes electrons to migrate in the reverse direction, from the floating gate of the storage transistor to its drain.
Thus, to carry out a memory cell write or erasure step, a high erasure or programming voltage of about 15 to 20 V needs to be available. This voltage is applied to either electrode of the storage transistor of the memory cell, depending on the operation to be performed.
However, the oxide layer between the floating gate and the drain of the storage transistor is thin and brittle. Thus, when the voltage applied to the electrodes of the storage transistor is greater than what is called the tunnel voltage, it should not vary sharply. Indeed, any sharp variation in the voltage leads to the creation of high current between the floating gate and the drain or source of the transistor. An excessive current would make the oxide layer brittle and could even damage it.
It may be recalled that the tunnel voltage is the minimum voltage needed for a charge to travel by the tunnel effect through the oxide layer, between the floating gate and the drain of a floating gate transistor. Typically, the value of the tunnel voltage is in the range of 10 V.
To obtain a voltage that varies gradually and slowly, the classic method is to use an erasure or programming circuit, a known example of which is shown in a diagrammatic view in FIG. 1a. This circuit 100 has a voltage step-up circuit 101, a voltage ramp production circuit 102 and a shaping circuit 103. All three are powered with a low power supply voltage VDD (not shown in FIG. 1a) in the range 2 to 3 V for 0.25 xcexcm technology.
The voltage step-up circuit 101 is, for example, a charge pump type of circuit. It produces a high voltage HIV of about 15 to 20 V from the low power supply voltage VDD. The circuit 102 produces a ramp voltage RAMP from the high voltage HIV. This ramp voltage RAMP has, for example, the shape shown by the unbroken line in FIG. 1b. The ramp voltage RAMP includes a rising phase 110 during which the voltage RAMP rises continuously up to its maximum value VMAX, which is, for example, equal to the high voltage HIV. This is followed by a voltage plateau 111 during which the voltage RAMP is constant, that is, equal to the value VMAX. There is a voltage drop 112 after the voltage plateau 111.
The ramp generation circuit 102 conventionally comprises a circuit for the charging and discharging of a power capacitor. The circuit is powered by a current source that gives a reference current IREF. The rising phase 110 of the voltage RAMP is obtained by charging a capacitor with a charging current ICH. The voltage plateau 111 for its part is obtained by the discharging of this capacitor with a discharging current IDECH.
The charging and/or discharging current used are most usually, but not necessarily, proportional to the reference current IREF and are constant. They are usually different from one another. The rising phase 110 may be lengthier or shorter than the voltage plateau 111, depending on the value of the current ICH with respect to the value of the current IDECH. The rising phase 110 and the voltage plateau 111 have a total duration TRAMP that corresponds to the duration of an erasure or programming operation.
An appropriate choice of the capacitance of the capacitor as well as the reference current IREF optimizes the slope of the rising phase 110 including the total duration TRAMP. This choice is generally a compromise based on the following criteria. When the voltage applied to the electrodes of the storage transistor is higher than the tunnel voltage, it must not vary sharply. For this purpose, the slope of the rising phase 110 must not cross a boundary value.
The total duration TRAMP must be sufficiently long for the voltage TRAMP to have the time to reach its maximum value VMAX. The voltage plateau must last long enough to ensure the full completion of an erasure or programming step, and the total duration TRAMP must be as small as possible.
The shaping circuit 103 receives the voltage RAMP and produces a high erasure or programming voltage VPP that is applied to either electrode of the memory cell (not shown in FIG. 1a), depending on whether the memory cell is to be erased or programmed. The high erasure or programming voltage VPP has, for example, the shape shown by the dashes in FIG. 1b. 
This shape includes a first voltage plateau 115, during which the voltage VPP is equal to the low supply voltage VDD, and a rising phase 116 followed by a second voltage plateau 117. The voltage VPP is equal to the voltage RAMP, minus a drop in voltage VTN in a transistor. The shape also includes a drop in voltage 118, during which the voltage VPP falls back to the voltage VDD.
The voltage VPP thus follows the variations in the voltage RAMP, minus a drop in voltage VTN of about 2 V, which corresponds approximately to the conduction threshold voltage of an N-type transistor. During a programming of a memory cell, zero voltage is applied to a control gate of a floating-gate transistor, a voltage equal to VPP is applied to the drain of the transistor, and its source is left at a floating potential. The current ID flowing between the drain and the source of the transistor has, in this case, the shape shown in FIG. 1c. 
The current ID is zero when the voltage VPP is rising, and is smaller than the tunnel voltage. Then it rises sharply (ref. 120) from zero up to a maximum value IDMAX when VPP crosses the tunnel voltage. The value IDMAX is reached when VPP reaches its maximum value VPPMAX. The current ID then falls again (ref. 121) throughout the duration of the plateau 117, then it drops sharply to zero (ref. 122) when the voltage VPP drops (118) to its minimum value VDD. During an erasure of the memory cell, the current flowing between the drain and the source has a similar shape. It flows simply in the reverse direction to that of its flow in the case of a programming operation.
The erasure time TER (or programming time TWR) of the memories is in the range of about 3 ms. The memory 7 erasure or programming time is thus relatively long. This may be particularly damaging in certain cases. For example, during the manufacture of the memories, all the cells of the memory are especially subjected to an endurance test. This endurance test generally includes the successive execution of several erasure and/or programming operations (about 500 such operations) to verify whether the cells have been properly manufactured, and if they meet the required specifications, especially in terms of durability.
This endurance test is only one among all the tests performed when making a memory. However, this test alone is particularly lengthy since it lasts about 2 seconds, which amounts to about half of the total duration of a full phase for testing a memory.
In view of the foregoing background, an object of the present invention to reduce the time of erasure or programming of a memory cells without harming the quality of the cell. This, in particular, would greatly reduce the duration of the endurance test for a memory when it comes off the production line.
The invention thus relates to a circuit for the production of a voltage for the erasure or programming of a memory cell. The circuit comprises a capacitor, and a discharge circuit connected to a first terminal of the capacitor to discharge the capacitor.
According to the invention, the circuit to discharge the capacitor comprises a first transistor, a drain of which is connected to the first terminal of the capacitor, and to activate the discharge circuit when a discharge signal is applied to the control gate of the first transistor. A slow discharge arm is connected to the source of the first transistor to produce a low current for discharging the capacitor when the discharge signal is received. A fast discharge arm is connected to the source of the first transistor, to produce a current for the fast discharging of the capacitor when the discharge signal and an operating mode selection signal are received simultaneously.
Thus, according to the invention, a discharge current IDECH is used. This current takes two values. This makes it possible, depending on the value used, to preserve or to reduce (or even eliminate) the plateau of the voltages RAMP, VPP, since the duration of the plateau is proportional to the value of the current IDECH. The choice of either of the values of the current IDECH is made by the user.
The circuit for the production of an erasure or programming voltage for a memory cell according to the invention works as follows. It is activated when it receives the discharge signal. Furthermore, if no mode selection signal is received, the circuit according to the invention is in a standard operating mode, and its operation in this case is similar to that of a prior art circuit.
In particular, the capacitor is discharged when the discharge signal is received in conditions similar to that of the capacitor of a prior art circuit, and the duration of the corresponding plateau is of the same magnitude. For this purpose, the discharge current chosen is a slow discharge current of the same magnitude as the discharge current used in a prior art circuit.
However, if a selection signal is received, then the circuit according to the invention is in a specific operating mode. In this case, the capacitor is discharged very rapidly, to reduce or eliminate the plateau phase and thus reduce the erasure or programming time. The fast discharging arm gives a high discharging current for this purpose. This current is, for example, 20 to 40 times the low discharge current produced by the slow discharging arm.
Reducing or eliminating the plateau of course similarly reduces the duration of any step for the erasure or programming of a memory cell. By choosing an adequate high discharge current, it is thus possible to halve the duration of such a step.
In the event of a total elimination of the plateau, the erasure of the programming of a cell is ensured only up to about 70 percent. This may be troublesome for certain applications, but not for every application. For example, in a normal mode of operation of a memory cell, it is important to ensure full programming in order to ensure, first, efficient preservation of data over time and, second, accurate read operations if necessary.
Conversely, to perform an endurance test on a memory cell, it is not indispensable to carry out a full erasure or programming of the cell. It is enough that the erasure or programming voltage applied and the current in the cell created by this voltage should reach their maximum values. The goal of this test indeed is only to watch the behavior, over time, of a cell when it undergoes high voltage and/or high current.
The circuit for the production of a voltage for the erasure or programming of a memory cell of the invention can thus be used to carry out different types of erasure or programming of memory cells, as efficiently as possible, especially in terms of time, voltages applied, currents created, etc.
The slow discharge arm comprises, for example, a second transistor, having a drain connected to the source of the first transistor and having a source connected to the ground of the circuit. The low discharge current is proportional to a reference current applied to the control gate of the second transistor. The second transistor may also be replaced by a series of parallel-connected transistors.
The fast discharge arm comprises, for example, a third transistor having one drain connected to the source of the first transistor, with the mode selection signal being applied to the control gate of the third transistor. The fast discharge arm also comprises a fourth transistor having one drain connected to a source of the third transistor, and having one source connected to the ground of the circuit. The reference current is applied to the control gate of the fourth transistor. The fourth transistor may also be replaced by a series of parallel-connected transistors.
The size of the fourth transistor (in terms of the gate width-to-length or W/L ratio) is greater than the size of the second transistor. Thus, the current across the fourth transistor, when it is on, is greater than the current across the second transistor. For example, the size of the fourth transistor is 10 to 100 times greater than the size of the second transistor.
According to another embodiment of the invention, the circuit for the production of a voltage for the erasure or programming of a memory cell also comprises a charging circuit, connected to a second terminal of the capacitor, to charge the capacitor. This charging circuit comprises a slow charging arm connected to the second terminal of the capacitor to produce a low charging current when an activation signal is received.
A fast charging arm is connected to the second terminal of the capacitor to produce a high charging current for the capacitor if the mode selection signal and a voltage level signal are received simultaneously. The voltage level signal indicates that an erasure or programming voltage given by the circuit for the production of an erasure or programming voltage is below a threshold voltage.
Thus, a charging of the capacitor is obtained, and therefore, a rise in the erasure or programming voltage varies according to the mode of operation of the circuit. When the mode selection signal is inactive, the rise in the programming or erasure voltage is slow, along only one slope. When the mode selection signal is active, the rise in the programming or erasure voltage takes place along two slopes.
One is a steep slope when the erasure or programming voltage is below a threshold value, or otherwise, it is a gentle slope. Thus, when the voltage becomes greater than the threshold voltage, its rise is similar to that of a standard operation (inactive mode selection signal). This makes it possible to avoid making excessively fast variations in the voltage applied to the oxides of the memory cell when this voltage has exceeded the tunnel voltage of the cell.
According to yet another embodiment, the circuit of the invention for the production of an erasure or programming voltage also comprises a circuit for the generation of a voltage ramp to produce a voltage ramp from potentials at the first terminal and the second terminal of the capacitor, and a shaping circuit comprising an eighth transistor. A high voltage is applied to a terminal of the eighth transistor, and the erasure or programming voltage is given at another terminal of the eighth transistor. The eighth transistor is preferably chosen to be a P-type transistor. The erasure or programming voltage may thus attain the value of the high voltage since a P-type transistor of this kind does not have any voltage drop at its terminals when it is on.
Finally, the invention also relates to a method for the production of voltage for the erasure or programming of a memory cell, during which a capacitor is charged by the application of a charging current to a second terminal during a first step. The capacitor is discharged by applying a discharge current to a first terminal of the capacitor during a second step. According to the invention, during the second step, the discharge current takes a low value, or a high value greater than the first value, as a function of a mode of operation.